The System Solutions Enablement team is looking for key talent to support our mission of enabling customers with system intellectual property (IP) solutions. This mission includes design and validation of re-usable, logically complex or performance critical IP that requires system level consideration when integrating into an ASIC. The team plays a key role in selecting, acquiring, designing, verifying and integrating intellectual property with a special focus towards reuse and quality.
Place of work: Bratislava, Mlynské nivy 14 (hybrid model: home office + office)
Working time: Flexible working hours
Salary: From 2 000 EUR, depends on candidate´s experience
Job description:
- Perform block and chip-level verification
- Work with design teams to develop verification plan/strategy
- Develop tests, verification components e.g. monitors and run regressions
- Debugging and correcting functional errors in the RTL, using simulation tools, debug tools, and programming skills
- Defining and implementing functional coverage, and enhancing the testbench to ensure coverage closure
- Documenting test plans and testbench design
Requirements:
- BS degree in Electrical Engineering or related field
- At least 2 years of digital verification experience
- Knowledge of Verilog or System Verilog
- Familiar with scripting language like Python/Perl
- Good command of English
